Recent years have witnessed a proliferation of portable devices, such as set-top boxes, cell phones, music players, video players, and cameras. Many of these devices include memory media for storing information. The memory media (internal or external, such as non-volatile memory cards such as SD cards) may be accessible by the portable device itself, or by an external device such as a PC. Accessing the memory media (as by the processor and/or the external device), however, has not been generally available at high-speed due to design limitations in portable devices.
Typically, memory media, such as flash cards are connected to the processor through input/output, control, and data ports (often having 10-20 or more pins) using a NAND bus, such as the Inter-Integrated Circuit (I2C) bus or the Serial Peripheral Interface (SPI) bus. These buses present a hard bandwidth limit of 60 Mbits/sec, which may prove to be inadequate while transferring real time or bulk media. One major chip design consideration in the last decade has been size. Developers and manufacturers often endeavor to downsize portable devices for better usability and portability, and reduction in the number of data transfer pins can drastically affect the portable device's size.
Therefore, there remains a long-felt but unresolved need for a system or method that transfers data between a baseband processor and memory media at high-speed. There is a further need for a system or method that reduces processor chip size, thereby allowing manufacturers or developers to decrease device size, increasing their portability.